The present invention is related to a delay circuit for delaying a signal by a constant time. More specifically, the present invention is directed to a circuit technique capable of obtaining a delay time in correspondence with a time constant which is determined based upon both a resistive element and a capacitance element.
FIG. 8 indicates an example of an arrangement of a related delay circuit. In this drawing, an input signal SIN is applied to an input portion of an inverter 301, and an input portion of another inverter 302 is connected to an output portion of this inverter 301. An output portion of the inverter 302 is connected to an inverting input terminal (−) of an operational amplifier 304 via a delay path 303 which is constructed of a resistive element 303A and a capacitive element 303B. A resistive element 304A for feedback purpose is connected between an output portion of the operational amplifier 304 and a non-inverting input terminal (+) thereof, and also, this non-inverting input terminal (+) is biased to a reference voltage “VREF” via a resistive element 304B. These operational amplifier 304 and resistive elements 304A, 304B may function as a comparator having a hysteresis characteristic with respect to a signal which is inputted to the non-inverting input terminal (−) of the operational amplifier 304. In other words, this comparator represents a high input logic threshold value “VTH” with respect to such an input signal whose signal level is transited to a high level, whereas this comparator represents a low input logic threshold value “VTL” with respect to such an input signal whose signal level is transited to a low level.
Next, operations of the above-described related delay circuit will now be explained with reference to a waveform diagram shown in FIG. 9.
First, under initial condition, the signal level of the input signal SIN is a low level, and a signal level of a signal S31 output from the inverter 301 into which this signal SIN is inputted is a high level. As a consequence, a signal level of a signal S33 appearing on the delay path 303 which is driven by the inverter 302 is a low level, whereas a signal level of a signal S34 output from the operational amplifier 304 into which this signal S33 having the low level is inputted is a high level. When the input signal SIN having; the low level is transited to a high level from this condition, the signal level of the signal S31 is transited to a low level, and also, the signal level of the signal S32 is transited to a high level. As a result, the signal S33 starts to ascend at a rate corresponding to the time constant which is determined based upon both the resistive element 303A and the capacitive element 303B. Then, when the signal S33 exceeds the high input logic threshold value VTH of the comparator constituted by the operational amplifier 304, the signal level of the signal S34 output from this operational amplifier 304 is transited to a low level.
Subsequently, when the signal level of the input signal SIN is transited to a low level, the low level of the signal S31 is transited to a high level, and the signal-level of the signal S32 is transited to a low level. When the signal level of this signal S32 is transited to the low level, the signal S33 starts to descend at the rate corresponding to the time constant which is determined based upon both the resistive element 303A and the capacitive element 303B. Then, when the signal S33 becomes lower than the low input logic threshold value VTL of the comparator constituted by the operational amplifier 304, the signal level of the signal S34 output from this operational amplifier 304 is transited to a high level. As previously explained, the signal S34 is delayed by such a delay time defined in the delay path 303 with respect to the input signal SIN, and then, the delayed signal S34 responds. It should be understood that delay components other than the delay component of the delay path 303 are neglected.
On the other hand, the above-explained related delay circuit owns such a problem that the delay time is changed in accordance with switching timing of the input signal SIN as the case may be. This problem will now be concretely explained. That is, the delay time of the output signal S34 with respect to the input signal SIN is given as such a time duration defined so that the signal S33 has started to be changed and thereafter reaches either the high input logic threshold value VTH or the low input logic threshold value VTL of the comparator which is constituted by the operational amplifier 304. In this case, assuming now that the signal S33 has previously reached the saturation condition before the input signal SIN is switched, an initial voltage when the signal S33 starts to be changed in response to the input signal SIN may be defined as either the power supply potential “VDD” or the ground potential “VSS”, and also, a potential difference from this initial voltage up to the low input logic threshold voltage VTL irrespective of the switching timing of the input signal SIN. In this case, since the signal S33 is changed by a constant potential difference and based upon a predetermined time constant, the resulting delay time may become constant.
In contrast to this delay time, when the input signal SIN is switched under such a condition that the signal S33 has not yet been saturated (namely, half way of transition), such an initial voltage when the signal S33 newly starts to be changed in response to the input signal SIN is varied in response to this switching timing of the input signal SIN. As a result, a potential difference defined from the initial voltage of the signal S33 up to the input logic threshold value of the comparator does not become constant, and the time defined until the level of the signal S33 reaches the input logic threshold value may be varied in accordance with the switching timing of the input signal SIN. As a consequence, a delay time of the output signal S34 with respect to the input signal SIN does not become constant.